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1 of 21 rev: 010307 general description the ds1386 is a nonvolatile static ram with a full-function real-time clock (rtc), alarm, watchdog timer, and interval timer that are all accessible in a byte-wide format. the ds1386 contains a lithium energy source and a quartz crystal, which eliminates the need for any external circuitry. data contained within 8k or 32k by 8-bit memory and the timekeeping registers can be read or written in the same manner as byte-wide static ram. the timekeeping registers are located in the first 14 bytes of memory space. data is maintained in the ramified timekeeper by intelligent control circuitry, which detects the status of v cc and write protects memory when v cc is out of tolerance. the lithium energy source can maintain data and real time for over ten years in the absence of v cc . timekeeper information includes hundredths of seconds, seconds, minutes, hours, day, date, month, and year. the date at the end of the month is automatically adjusted for months with less than 31 days, including correction for leap year. the ramified timekeeper operates in either 24- hour or 12-hour format with an am/pm indicator. the watchdog timer provides alarm interrupts and interval timing between 0.01 seconds and 99.99 seconds. the real-time alarm provides for preset times of up to one week. interrupts for both watchdog and rtc operate when the system is powered down. either can provide system ?wake- up? signals. features 8kb or 32kb of user nv ram integrated nv sram, real-time clock, crystal, power-fail control circuit, and lithium energy source totally nonvolatile with over 10 years of operation in the absence of power watchdog timer restarts an out-of- control processor alarm function schedules real-time related activities su ch as system wakeup programmable interrupts and square- wave output all registers are individually addressable via the address and data bus interrupt signals are active in power- down mode pin configurations appear at end of data sheet. ordering information part temp range voltage (v) pin-package top mark ds1386 -8-120 0c to +70c 5.0 32 emod (0.740 ) ds1386-8k-120 ds1386-8-120+ 0c to +70c 5.0 32 emod (0.740 ) ds1386-8k+120 ds1386-32-120 0c to +70c 5.0 32 emod (0.740 ) ds1386-32k-120 ds1386-32-120+ 0c to +70c 5.0 32 emod (0.740 ) ds1386-32k+120 ds1386p -8-120 0c to +70c 5.0 34 powercap* ds1386p-8k-120 ds1386p-8-120+ 0c to +70c 5.0 34 powercap* ds1386p+8k-120 DS1386P-32-120 0c to +70c 5.0 34 powercap* ds1386p-32k-120 DS1386P-32-120+ 0c to +70c 5.0 34 powercap* ds1386p+32k-120 + denotes a lead-free/rohs-compliant device. * ds9034pcx powercap required (must be ordered separately). ds1386/ds1386p ramified watchdog timekeepe r www.maxim-ic.com
ds1386/1386p 2 of 21 pin description pin emod powercap 8k x 8 32k x 8 8k x 8 32k x 8 name function 1 1 34 34 inta active-low interrupt output a (open drain) 2 2 1 1 intb active-low interrupt output b (open drain) 3, 28 ? 2, 3, 31, 32 2, 3 n.c. no connection 12 12 18 18 a0 11 11 19 19 a1 10 10 20 20 a2 9 9 21 21 a3 8 8 22 22 a4 7 7 23 23 a5 6 6 24 24 a6 5 5 25 25 a7 27 27 26 26 a8 26 26 27 27 a9 23 23 28 28 a10 25 25 29 29 a11 4 4 30 30 a12 ? 28 ? 31 a13 ? 3 ? 32 a14 address inputs 16 16 17 17 gnd ground 13, 14, 15, 17? 21 13, 14, 15, 17? 21 16?9 16?9 dq0, dq1, dq2, dq3? dq7 data input/output 22 22 8 8 ce active-low chip enable 24 24 7 7 oe active-low output enable 29 29 6 6 we active-low write enable 30, 32 30, 32 ? ? v cc +5v power supply 31 31 33 33 sqw square-wave output ? ? 4 4 pfo active-low power-fail output ? ? x1, x2 crystal connections ? ? v bat battery connection
ds1386/1386p 3 of 21 packages the ds1386 is available in two packages (32-pin encapsulated dip module and 34-pin powercap module). the 32-pin dip style module integrates the cr ystal, lithium energy source, and silicon all in one package. the 34-pin powercap module board is design ed with contacts for connection to a separate powercap (ds9034pcx) that contains the crystal and battery. this design allows the powercap to be mounted on top of the ds1386p after the completi on of the surface mount process. mounting the powercap after the surface mount process prevents damage to the crystal and battery due to high temperatures required for solder reflow. the powe rcap is keyed to prevent reverse insertion. the powercap module board and powercap are ordered sepa rately and shipped in separate containers. the part number for the powercap is ds9034pcx. operation?read registers the ds1386 executes a read cycle whenever we (write enable) is inactive (high), ce (chip enable) and oe (output enable) are active (low). the unique ad dress specified by the a ddress inputs (a0-a14) defines which of the registers is to be accessed. valid data will be available to the eight data output drivers within t acc (access time) after the last address- input signal is stable, providing that ce and oe access times are also satisfied. if oe and ce access times are not satisfied, then data access must be measured from the latter occurring signal ( ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than address access. operation?write registers the ds1386 is in the write mode whenever the we (write enable) and ce (chip enable) signals are in the active (low) state after the address inputs ar e stable. the latter occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is termin ated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery state (t wr ) before another cycle can be initiated. data must be valid on the data bus with sufficient data set-up (t ds ) and data hold time (t dh ) with respect to the earlier rising edge of ce or we . the oe control signal should be kept inactive (high) during write cy cles to avoid bus contention. however, if the output bus has been enabled ( ce and oe active), then we will disable the outputs in t odw from its falling edge. data retention the ramified timekeeper provides full functional capability when v cc is greater than 4.5v and write- protects the register contents at 4.25v typical. data is maintained in the absence of v cc without any additional support circuitry. the ds1386 constantly monitors v cc . should the supply voltage decay, the ramified timekeeper will automatical ly write-protect itself and all inpu ts to the registers become ?don?t care.? the two interrupts inta and intb (intb) and the internal cloc k and timers continue to run regardless of the level of v cc . however, it is important to insure that the pull-up resistors used with the interrupt pins are never pulled up to a value that is greater than v cc + 0.3v. as v cc falls below approximately 3.0v, a power-switching circuit turns the internal lithium energy so urce on to maintain the clock and timer data and functionalit y. it is also required to insure th at during this time (battery backup mode), the voltage present at inta and intb (intb) never exceeds 3.0v. during power-up, when v cc rises above approximately 3.0v, the power switching circuit connects external v cc and disconnects the internal lithium energy source. no rmal operation can resume after v cc exceeds 4.5v for a period of 200ms.
ds1386/1386p 4 of 21 ramified timekeeper registers the ramified timekeeper has 14 registers, which are 8 bits wide that contain all of the timekeeping, alarm, and watchdog and control information. the cl ock, calendar, alarm, and watchdog registers are memory locations, which contain external (user-accessi ble) copies of the timekeeping data. the external copies are independent of internal functions except that they are upda ted periodically by the simultaneous transfer of the incremented internal copy (see figure 1). the command re gister bits are affected by both internal and external functions. th is register will be discussed late r. the 8 or 32kbytes of ram and the 14 external timekeeping registers ar e accessed from the external address and data bus. registers 0, 1, 2, 4, 6, 8, 9, and a contain time of day and date information (see figure 2). time of day information is stored in bcd. registers 3, 5, and 7 cont ain the time of day alarm information. time of day alarm information is stored in bcd. register b is the co mmand register and informati on in this register is binary. registers c and d are the watchdog alarm re gisters and information, wh ich is stored in these two registers, is in bcd. registers e through 1fff or 7fff are user bytes and can be used to maintain data at the user?s discretion. clock accuracy (dip module) the ds1386 is guaranteed to keep time accuracy to within 1 minute per month at +25c. clock accuracy (p owercap module) the ds1386p and ds9034pcx are each individually te sted for accuracy. once mounted together, the module is guaranteed to k eep time accuracy to within 1.53 minutes per month (35ppm) at +25 c.
ds1386/1386p 5 of 21 figure 1. block diagram
ds1386/1386p 6 of 21 time-of-day registers registers 0 through a contain time, da te, and alarm data in bcd. fifteen bits within these 11 registers are not used and will always read 0 regardless of how th ey are written. bits 6 and 7 in the months register (9) are binary bits. when set to logic 0, eosc (bit 7) enables the rtc oscillat or. this bit is set to logic 1 as shipped from dallas semiconductor to preven t lithium energy consumption during storage and shipment (dip module only). this bit will normally be turned on by the user during device initialization. however, the oscillator can be turned on and off as n ecessary by setting this bit to the appropriate level. bit 6 of this same byte controls the square wave out put. when set to logic 0, the square wave output pin will output a 1024hz square wave signal. when set to logic 1 the square wave output pin is in a high impedance state. bit 6 of the hours register is defined as the 12- or 24-hour select bit. when set to logic 1, the 12-hour format is selected. in the 12-hour format , bit 5 is the am/pm bit w ith logic 1 being pm. in the 24-hour mode, bit 5 is the second 10-hour bit ( 20-23 hours). the time of day registers are updated every 0.01 seconds from the real time clock, except wh en the te bit (bit 7 of regi ster b) is set low or the clock oscillator is not runni ng. the preferred method of synchroniz ing data access to and from the ramified timekeeper is to access the command register by doing a wr ite cycle to address location 0b and setting the te bit (transfer enable bit) to a lo gic 0. this will freeze the external time of day registers at the present recorded time, allowing access to occur without dange r of simultaneous update. when the watch registers have been read or writte n, a second write cycle to location 0b, setting the te bit to a logic 1, will put the time of day registers back to being updated every 0.01 second. no time is lost in the real time clock because the internal copy of the time of day register buffers is continually incremented while the external memory registers ar e frozen. an alternate method of reading and writing the time of day registers is to ignore synchroni zation. however, any single read may give erroneous data as the real time clock may be in the process of updating the external memory registers as data is being read. the internal copies of seconds through years are incremen ted, and the time of day alarm is checked during the period that hundreds of seconds reads 99 and are tr ansferred to the external register when hundredths of seconds roll from 99 to 00. a way of making sure data is valid is to do multiple reads and compare. writing the registers can also produce erroneous results for the same reasons. a way of making sure that the write cycle has caused proper update is to do read verifies and re-e xecute the write cycle if data is not correct. while the possibility of erroneous results from reads and write cycles has been stated, it is worth noting that the probability of an incorrect result is kept to a minimum due to the redundant structure of the ramified timekeeper. time-of-day alarm registers registers 3, 5, and 7 contain the time of day alar m registers. bits 3, 4, 5, and 6 of register 7 will always read 0 regardless of how they are written. b it 7 of registers 3, 5, and 7 are mask bits (table 1). when all of the mask bits are logic 0, a time of day alarm will only occur when registers 2, 4, and 6 match the values stored in registers 3, 5, and 7. an alarm will be generated every day when bit 7 of register 7 is set to a logic 1. similarly, an alarm is generated every hour when bit 7 of registers 7 and 5 is set to a logic 1. when bit 7 of registers 7, 5, and 3 is set to a logic 1, an alarm will occur every minute when register 1 (seconds) rolls from 59 to 00. time of day alarm register s are written and read in the same form at as the time of day registers. the time of day alarm flag and interrupt are always cl eared when alarm register s are read or written.
ds1386/1386p 7 of 21 watchdog alarm registers registers c and d contain the time for the watchdog alarm. the two registers contain a time count from 00.01 to 99.99 seconds in bcd. the value written into the watchdog alarm regist ers can be written or read in any order. any access to re gister c or d will cause the watchdog alarm to reinitialize and clears the watchdog flag bit and the watc hdog interrupt output. when a new va lue is entered or the watchdog registers are read, the watchdog timer will start count ing down from the entere d value to zero. when zero is reached, the watchdog interrupt output will go to the active state. the watchdog timer countdown is interrupted and reinitialized back to the entered value every time either of the registers are accessed. in this manner, controlled periodic accesses to th e watchdog timer can prevent the watchdog alarm from going to an active level. if access does not occur, countdown alarm will be repetitive. the watchdog alarm registers always read the en tered value. the actual countdown re gister is internal and is not readable. writing registers c and d to 0 will disable the wa tchdog alarm feature.
ds1386/1386p 8 of 21 figure 2. ds1386 ramified watchdog timekeeper registers table 1. time-of-day alarm mask bits register (3) minutes (5) hours (7) days description 1 1 1 alarm once per minute 0 1 1 alarm when minutes match 0 0 1 alarm when hours and minutes match 0 0 0 alarm when hours, minutes and days match note: any other bit combinations of mask bit settings produce illogical operation.
ds1386/1386p 9 of 21 command register address location 0bh is the command re gister where mask bits, control bits and flag bits reside. the operation of each bit is as follows: bit 7: te (transfer enable). this bit when set to a logic 0 will disable the transfer of data between internal and external clock registers. the contents in the external clock registers are now frozen and reads or writes will not be affected with updates. this bit must be set to a logic 1 to allow updates. bit 6: ipsw ( interrupt switch). when set to a logic 1, inta is the time of day alarm and intb/( intb ) is the watchdog alarm. when set to logic 0, this bit reverses the output pins. inta is now the watchdog alarm output and intb/( intb ) is the time of day alarm output. bit 5: ibh/lo ( interrupt b sink or source current). when this bit is set to a logic 1 and v cc is applied, intb/( intb ) will source current (see dc characteristics ioh). when this bit is set to a logic 0, intb will sink current (see dc characteristics iol). bit 4: pu/lvl (interrupt pulse mode or level mode). this bit determines whether both interrupts will output a pulse or level signal. when set to a logic 0, inta and intb/( intb ) will be in the level mode. when this bit is set to a logic 1, the pulse mode is selected and inta will sink current for a minimum of 3ms and then release. intb/( intb ) will either sink or source current, depending on the condition of bit 5, for a minimum of 3ms and then rele ase. intb will only source current when there is a voltage present on v cc . bit 3: wam (watchdog alarm mask). when this bit is set to a logic 0, the watchdog interrupt output will be activated. the activated state is determin ed by bits 1,4,5, and 6 of the command register. when this bit is set to a logic 1, the wa tchdog interrupt output is deactivated. bit 2: tdm (time-of-day alarm mask). when this bit is set to a logic 0, the time of day alarm interrupt output will be activated. the activated state is determined by bits 0,4,5, and 6 of the command register. when this bit is set to a logic 1, the time of day alarm interrupt output is deactivated. bit 1: waf (watchdog alarm flag). this bit is set to a logic 1 when a watchdog alarm interrupt occurs. this bit is read only. the bit is reset wh en any of the watchdog alarm registers are accessed. when the interrupt is in the pulse mode (see bit 4 de finition), this flag will be in the logic 1 state only during the time the interrupt is active. bit 0: tdf (time-of-day flag). this is a read-only bit. this bit is set to a logic 1 when a time of day alarm has occurred. the time the alarm occurred can be determined by reading the time of day alarm registers. this bit is reset to a logic 0 state when any of the time of day alarm registers are accessed. when the interrupt is in the pulse mode (see bit 4 de finition), this flag will be in the logic 1 state only during the time the interrupt is active.
ds1386/1386p 10 of 21 absolute maxi mum ratings voltage range on any pin relative to ground?????????????????..-0.3v to +7.0v operating temperature range????????????????????????...0c to +70c storage temperature range????????????????????????...-40c to +70c soldering temperature??????????..see ipc/jedec j-std-020 specification (see note 14) this is a stress rating only and functional ope ration of the device at these or any ot her conditions above those indicated in t he operation sections of this specification is not implied. exposure to absolute maximum ra ting conditions for extended periods of time may affect reliability. recommended dc oper ating conditions (t a = 0 c to +70 c) parameter symbol min typ max units notes supply voltage v cc 4.5 5.0 5.5 v 10 input logic 1 v ih 2.2 v cc + 0.3 v 10 input logic 0 v il -0.3 +0.8 v 10 dc electrical characteristics (v cc = 5.0v 10%, t a = 0 c to +70 c.) parameter symbol min typ max units notes input leakage current i il -1.0 +1.0 a output leakage current i lo -1.0 +1.0 a i/o leakage current i lio -1.0 +1.0 a output current at 2.4v i oh -1.0 ma output current at 0.4v i ol 2.1 ma 13 standby current ce = 2.2v i ccs1 3.0 7.0 ma standby current ce = v cc - 0.5 i ccs2 2.0 4.0 ma active current i cc 85 ma write protection voltage v tp 4.0 4.25 4.5 v capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 7 15 pf output capacitance c out 7 15 pf input/output capacitance c i/o 7 15 pf
ds1386/1386p 11 of 21 ac electrical characteristics (v cc = 5.0v 10%, t a = 0 c to 70 c.) ds1386xx-120 parameter symbol min max units notes read cycle time t rc 120 ns 1 address access time t acc 120 ns ce access time t co 120 ns oe access time t oe 100 ns oe or ce to output active t coe 10 ns output high-z from deselect t od 40 ns output hold from address change t oh 10 ns write cycle time t wc 120 ns write pulse width t wp 110 ns 3 address setup time t aw 0 ns write recovery time t wr 10 ns output high-z from we t odw 40 ns output active from we t oew 10 ns data setup time t ds 85 ns 4 data hold time t dh 10 ns 4, 5 inta , intb pulse width t ipw 3 ms 11, 12
ds1386/1386p 12 of 21 read cycle (note 1) write cycle 1 (notes 2, 6, 7) write cycle 2 (notes 2, 8)
ds1386/1386p 13 of 21 timing diagram?interrupt outputs pulse mode (see notes 11 and 12) power-down/power-up timing
ds1386/1386p 14 of 21 ac electrical characteristics power-up/power-down timing (t a = 0 c to +70 c) parameter symbol min max units notes ce high to power fail t pf 0 ns recovery at power-up t rec 200 ms v cc slew rate power-down t f 4.0 v cc 4.5v 300 s v cc slew rate power-down t fb 3.0 v cc 4.25v 10 s v cc slew rate power-up t r 4.5v v cc 4.0v 0 s expected data retention t dr 10 years 9 warning: under no circumstances are negati ve undershoots, of any amplitude, allowed when device is in battery-backup mode.
ds1386/1386p 15 of 21 notes: 1) we is high for a read cycle. 2) oe = v ih or v il . if oe = v ih during write cycle, the output buffe rs remain in a high impedance state. 3) t wp is specified as the logical and of the ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4) t ds or t dh are measured from the earlier of ce or we going high. 5) t dh is measured from we going high. if ce is used to terminate the write cycle, then t dh = 20ns for -120 parts and t dh = 25ns for -150 parts. 6) if the ce low transition occurs simultaneously with or later than the we low transition in write cycle 1, the output buffers remain in a high impedance state during this period. 7) if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high impedance state during this period. 8) if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a hi gh impedance state during this period. 9) each ds1386 is marked with a four-digit date code aabb. aa de signates the year of manufacture. bb designates the week of manufacture. the expected t dr is defined for dip m odules as starting at the date of manufacture. 10) all voltages are referenced to ground. 11) applies to both interrupt pins when the alarms are set to pulse. 12) interrupt output occurs within 100ns on the alarm condition existing. 13) both inta and intb ( intb ) are open-drain outputs. 14) real-time clock modules (dip) can be successfu lly processed through conventional wave-soldering techniques as long as temperatur e exposure to the lithium energy s ource contained within does not exceed +85c. post solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used. in addition, for the powercap version: a. dallas semiconductor recommends that powerc ap module bases experience one pass through solder reflow oriented with the label side up (?live-bug?). b. hand soldering and touch-up: do not touch or a pply the soldering iron to leads for more than 3 seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder.
ds1386/1386p 16 of 21 ac test conditions ac test conditions input levels: 0v to 3v output load: 50pf + 1ttl gate transition times: 5ns input pulse levels: 0 to 3.0v timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5ns pin configurations v cc inta 13 1 2 3 4 5 6 7 8 9 10 11 12 14 31 8k x 8 encapsulated module n.c. a7 a5 a4 a3 a2 a1 a0 dq1 dq0 v cc s q w w e n.c. a 8 a 9 a 11 o e a 10 c e dq7 dq5 dq6 32 30 29 28 27 26 25 24 23 22 21 19 20 i nt b a12 a6 dq2 gnd 15 16 18 17 dq4 dq3 ds1386 i nt a 32k x 8 encapsulated module 13 1 2 3 4 5 6 7 8 9 10 11 12 14 31 v cc 32 30 29 28 27 26 25 24 23 22 21 19 20 15 16 18 17 v cc s q w w e a 13 a 8 a 9 a 11 o e a 10 c e dq7 dq5 dq6 dq4 dq3 a14 a7 a5 a4 a3 a2 a1 a0 dq1 dq0 i nt b a12 a6 dq2 gnd ds1386 1 i ntb ( intb ) 2 3 n.c. n.c. p f o v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 sqw n.c. 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 n.c. a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 34 i nta x1 gnd v bat x2 8k x 8 powercap? module board (uses ds9034pcx powercap) 1 i ntb ( intb ) 2 3 n.c. n.c. p f o v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 sqw a 14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 34 i nta x1 gnd v bat x2 32k x 8 powercap module board (uses ds9034pcx powercap) ds1386p ds1386p top view
ds1386/1386p 17 of 21 package information (the package drawing(s) in this data sheet may not reflect t he most current specifications . for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .)
ds1386/1386p 18 of 21 package information (continued) (the package drawing(s) in this data shee t may not reflect the most current specif ications. for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .)
ds1386/1386p 19 of 21 package information (continued) (the package drawing(s) in this data sheet may not reflect t he most current specifications . for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .)
ds1386/1386p 20 of 21 package information (continued) (the package drawing(s) in this data shee t may not reflect the most current specif ications. for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .)
ds1386/1386p 21 of 21 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2007 maxim integrated products the maxim logo is a registered trademark of maxim integrated produ cts, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. package information (continued) (the package drawing(s) in this data sheet may not reflect t he most current specifications . for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .)

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